Conventionally, interconnections, as of the gate electrodes, etc. of MOSFETs have been patterned by one photolithography process. However, as the semiconductor integrated circuits have been more downsized, effects, such as the rounding and shortening of the end parts of narrow interconnections, due to the optical proximity effect, etc., have become conspicuous. It has been difficult to control the configurations of the end parts of the interconnections.
In such background, recently multiple patterning techniques are used to control with high precision the configurations of the end parts of the interconnections. In the typical multiple patterning technique, interconnections are patterned by combining a processing with a first mask pattern for forming narrow lines and a processing with a second mask patterns for cutting the narrow lines to form the end parts of the interconnections.
On the other hand, the gate insulating film and the gate electrode of the MOSFETs have been formed of the combination of a high dielectric constant insulating film of higher dielectric constant, and a metal film in place of the combination of silicon oxide film formed by thermally oxidizing a silicon substrate, and polycrystalline silicon film.
The followings are examples of related: Japanese Laid-open Patent Publication No. 2003-303963; Japanese Laid-open Patent Publication No. 2011-228395; and Japanese Laid-open Patent Publication No. 2012-044184.
In order to suppress the corrosion of the gate insulating film and the gate electrode with the chemical treatment in the manufacturing process, often the gate insulating film and the gate electrode are covered with a silicon oxide film, a silicon nitride film or a polycrystalline silicon film. However, the inventor of the present application has found for the first time the problem that in forming the gate electrode by the multiple patterning described above, the gate insulating film and the gate electrode are often exposed by once chemical treatment or processing in the manufacturing process and are corroded by the chemical treatment or processing in the following manufacturing process. This problem takes place with the gate insulating film and the gate electrode formed respectively of high dielectric constant insulating film and metal film.